A comparator is used to compare two voltages and produce a digital output signal based on the comparison result. Filters, on the other hand, are designed to allow certain frequencies to pass while attenuating others. During testing, for comparators, parameters such as hysteresis and response time are measured. For filters, characteristics like cutoff frequency, roll-off rate, and attenuation in the stopband are evaluated.
Fig. 7. Transient output waveform of the comparator.
Fig. 8. Amplitude-Frequency and Phase-Frequency Response Characteristics
of the Comparator. The blue curve represents the magnitude-frequency response,
while the red curve represents the phase-frequency response.
Comparators are widely used in applications such as analogto-
digital converters (ADCs), peak detection circuits, and overcurrent
detection circuits [21]. Comparators can be broadly
classified into two types: current comparators and voltage
This paper presents a chaotic integrated circuit based on a dual-delay voltage-controlled oscillator (VCO). To address the hardware limitations associated with the traditional Chua circuit using discrete components, the proposed circuit employs the SMIC 180 nm CMOS process to achieve full integration. A dual-delay VCO regulates the oscillation frequency, while an operational trans-impedance amplifier (OTA) controls the gain within the circuit. The chaotic behavior of the integrated circuit is evaluated using Lyapunov exponents, bifurcation diagrams, and phase diagrams.
This dataset contains the data used to create figures for the manuscript Robust Complementary Logic Using Multi-Gate N/MEMS Relays. This paper presents novel complementary logic gate structures and discusses failure modes and optimization methods for these devices. A detailed comparison of metallization schemes and operational modes is included as well. In this dataset, information used to generate figure 2 (a, b), 4, 5 (a), and 6 are contained herein. Figure 2 show cases the change in response time with variations in handle layer voltage. Figure 4 present
A novel ultra-low-voltage (ULV) Dual-EdgeTriggered (DET) flip-flop based on the True-Single-PhaseClocking (TSPC) scheme is presented in this paper. Unlike Single-Edge-Triggering (SET), Dual-Edge-Triggering has the advantage of operating at the half-clock rate of the SET clock. We exploit the TSPC principle to achieve the best energy-efficient figures by reducing the overall clock load (only to 8 transistors) and register power while providing fully static, contention-free functionality to satisfy ULV operation.
In the first four txt files, the first two numbers in the file name represent the phase change interval, while the third number represents the phase change step. For example, the first dataset shows that the phase ranges from 0 to 60° with a step size of 15°. In the fifth txt file, the Q value fluctuates between 2 and 4° with a phase step of 1°.
The dataset is derived from sampling Modbus commands in RS485 fieldbus networks, where the communication baud rate is 9.6k bit/s and the sampling frequency is set to 100 KS/s. In the dataset, 2000 signals are stored as normal data and abnormal data based on different intrusion devices in .xlsx format, respectively, with a total size of 170 MB. In this dataset, the attack scenario is the unauthorized insertion of a silent intrusion device into the fieldbus, thereby eavesdropping communication data.
Dataset Description
A dataset containing data collected from measuring the drift characteristics titanium dioxide memristors, for a variety of initial states, under zero-bias conditions.
The devices used were TiO2 devices, with Al2O3 interstitials - the same device type as used in [1].
Data Collection
Devices were electroformed using a series of steadily increasing voltage pulses, ranging in magnitude from 3V to 10V with a step of 0.5V. The electroforming pulse widths ranged from 10µs to 100µs.
The password for the zip files are in the articles which cite this dataset.
