In this brief, the impact of substrate bias (Vgb), on the electrical performance of silicon on insulator dopingless transistor (SOI-DLT) is analysed for analog applications. It is observed that SOI-DLTs are more immune to Vgb in contrast to its conventional counterpart SOI junctionless transistor (SOIJLT). When Vgb is increased from 2V to 8V, the variation in intrinsic gain (gmrO) of SOI-JLT is 81.69%, however, in the case of SOI-DLT, the gmrO variation is 5.37%. The insignificant variation in gmrO of SOI-DLT is found against Vgb than SOI-JLT due to the use of the lightly doped channel.

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This dataset analyzes a survey delivered in 2019 to 259 experts in engineering education that asked them to forecast which information and communication technologies were most likely to impact the practice of engineering education based on the expert's discipline (electrical, electronics, mechanical, telecommunications engineering, computer science, etc.) and region.

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