FPGA
A high-quality dataset is essential for validating the effectiveness and accuracy of the proposed compression method. To assess the feasibility of the research methodology, we collected neural signals from 96 channels recorded from two non-human primates using the Blackrock Microsystems system and the Blackrock Cerebus, with a sampling rate of 30 kHz.
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Field programmable gate array (FPGA) is becoming an attractive solution for real-time electromagnetic transient (EMT) simulations.
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The security of systems with limited resources is essential for deployment and cannot be compromised by other performance metrics such as throughput. Physically Unclonable Functions (PUFs) present a promising, cost-effective solution for various security applications, including IC counterfeiting and lightweight authentication. PUFs, as security blocks, exploit physical variations to extract intrinsic responses based on applied challenges, with Challenge-Response Pairs (CRPs) uniquely defining each device.
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This data set corresponds to Table II:UNIFORMITY OF TC-PUF DESIGN of manuscript titled "A Lightweight and Secure Physical Unclonable Function Design on FPGA". The provided data is for FPGA board No. 1 to 15. Board no. 1 to 14 represent uniformity of 40X40 TC-PUF response implemented on Artix-7 FPGA, and board no. 15 represent uniformity of 20X40 TC-PUF response implemented on Zynq Z-7010 FPGA. It is observed that nearly all the TC-PUF implemented on individual FPGAs have a slight bias towards ‘0’.
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Physically unclonable functions (PUFs) are foundational components that offer a cost-efficient and promising solution for diverse security applications, including countering integrated circuit (IC) counterfeiting, generating secret keys, and enabling lightweight authentication. PUFs exploit semiconductor variations in ICs to derive inherent responses from imposed challenges, creating unique challenge-response pairs (CRPs) for individual devices. Analyzing PUF security is pivotal for identifying device vulnerabilities and ensuring response credibility.
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Cacheaccel Simulator trace files and project files are uploaded.
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This repository includes the data collected from the aocl profile and the Jupyter notebooks with the memory model equations proposed. Application folder contains a set of benchmarks to validate the proposed model.
The model was developed using the Quartus aocl version 18.1 for Stratix10 GX and 19.4 for Stratix10MX
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With a large number of all-controlled switching devices of converters in MMC-HVDC system and the frequency-dependent characteristics of line impedance in the electromagnetic transient model of HVDC transmission line, the real-time simulation platform calls for subtle time step and high calculation accuracy. The calculation parameters are prestored in advance so that they can be obtained by looking up tables in the calculation process, which reduces the computational load of simulation calculation of MMC-HVDC system.
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