Cross-Architecture and Device PUF Dataset

Citation Author(s):
ENAS
ABULIBDEH
System on Chip Lab, Electrical Engineering and Computer Science, Khalifa University, Abu Dhabi 127788, UAE
Hani
Saleh
System on Chip Lab, Electrical Engineering and Computer Science, Khalifa University, Abu Dhabi 127788, UAE
Baker
Mohammad
System on Chip Lab, Electrical Engineering and Computer Science, Khalifa University, Abu Dhabi 127788, UAE
Mahmoud
Al-Qutayri
System on Chip Lab, Electrical Engineering and Computer Science, Khalifa University, Abu Dhabi 127788, UAE
Submitted by:
Enas Abulibdeh
Last updated:
Tue, 05/07/2024 - 13:16
DOI:
10.21227/2581-8y14
License:
0
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Abstract 

The security of systems with limited resources is essential for deployment and cannot be compromised by other performance metrics such as throughput. Physically Unclonable Functions (PUFs) present a promising, cost-effective solution for various security applications, including IC counterfeiting and lightweight authentication. PUFs, as security blocks, exploit physical variations to extract intrinsic responses based on applied challenges, with Challenge-Response Pairs (CRPs) uniquely defining each device. Security analysis based on CRPs evaluates the block's resistance against general and modeling-based attacks. This dataset comprises CRP sets collected from two different designs of digital-based PUFs implemented on a Field Programmable Gate Array (FPGA). For each design, the dataset was collected from 50 FPGAs using the same input challenge file. From each device, 5K records were collected for the first design and 10K records for the second design. Additionally, CRP sets under voltage or temperature variation were extracted from the same device, using the same input challenge under different environmental conditions.

Instructions: 

The dataset comprises two main folders, each corresponding to a distinct design of CRO PUF implemented and verified on FPGA. Within each folder, a challenges file (.txt) is provided, representing the inputs applied consecutively to each design. Responses from 50 FPGAs were collected under standard conditions (5V and 25°C) for each applied input file. Additionally, responses from a single FPGA were gathered under varying environmental conditions, including voltage and temperature fluctuations. The associated responses were recorded under these diverse conditions. To form Challenge-Response Pairs (CRPs), each input challenge and its corresponding response, situated at the same offset in both files, are systematically associated.

Funding Agency: 
Technology Innovation Institute (TII)
Grant Number: 
EX2021-005