Cacheaccel_Simulator

Citation Author(s):: Shivani
Shah

Nanditha
Rao
Submitted by:: Shivani Shah
Last updated:: Thu, 02/17/2022 - 04:58
DOI:: 10.21227/ad0c-ga03
License:: Creative Commons Attribution

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Categories:: Other
Keywords:: Cache, FPGA

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Abstract

Cacheaccel Simulator trace files and project files are uploaded.

Instructions:

These files need to be run with Xilinx Vivado 2019.1 version.

Dataset Files

Trace files provided as input to Cacheaccel spec_files.zip (115.40 MB)
Singlecore framework of Cacheaccel Singlecore_Cacheaccel.zip (118.48 MB)
Multicore framework of Cacheaccel Multicore_Cacheaccel.zip (147.75 MB)

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