Gate-Level RTL Description of the Glitch Optimized Multipliers

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This paper presents a novel implementation scheme

of the essential circuit blocks for high performance, full-precision

Booth multipliers leveraging a hybrid logic style. By exploiting

the behavior of parasitic capacitance of MOSFETs, a carefully

engineered design style is employed to reduce dynamic power dissipation

while improving the glitch immunity of the circuit blocks.

The circuit-level techniques along with the proposed signal-flow

optimization scheme prevent the generation and propagation

of spurious activities in both partial-product and adder-tree

stages. Two full-precision Booth multipliers built from proposed

strategies were compared to the state-of-the-art versions known

from literature by means of extensive post-layout simulations

in 65-nm CMOS technology. The proposed versions on average

demonstrated up to 10% and 30% power savings in general.


The front-end Verilog RTL description of the Glitch-Optimized multipliers are available in this dataset. These RTL files can be used for spice level, gate level or post layout level simulations.