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First Name:
Anuradha
Last Name:
Ranasinghe
Datasets & Competitions
A novel ultra-low-voltage (ULV) Dual-EdgeTriggered (DET) flip-flop based on the True-Single-PhaseClocking (TSPC) scheme is presented in this paper. Unlike Single-Edge-Triggering (SET), Dual-Edge-Triggering has the advantage of operating at the half-clock rate of the SET clock. We exploit the TSPC principle to achieve the best energy-efficient figures by reducing the overall clock load (only to 8 transistors) and register power while providing fully static, contention-free functionality to satisfy ULV operation.
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The cell characterization scripts and ultra low voltage flip-flop design information including 320-bit (16x20) parallel shift register design....
If you use this data, please add the citation to the following paper :
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This paper presents a novel implementation scheme
of the essential circuit blocks for high performance, full-precision
Booth multipliers leveraging a hybrid logic style. By exploiting
the behavior of parasitic capacitance of MOSFETs, a carefully
engineered design style is employed to reduce dynamic power dissipation
while improving the glitch immunity of the circuit blocks.
The circuit-level techniques along with the proposed signal-flow
optimization scheme prevent the generation and propagation
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373 Views