Glitch Optimized Circuit Blocks

This paper presents a novel implementation scheme

of the essential circuit blocks for high performance, full-precision

Booth multipliers leveraging a hybrid logic style. By exploiting

the behavior of parasitic capacitance of MOSFETs, a carefully

engineered design style is employed to reduce dynamic power dissipation

while improving the glitch immunity of the circuit blocks.

The circuit-level techniques along with the proposed signal-flow

optimization scheme prevent the generation and propagation