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First Name:
Li
Last Name:
Xiang
Datasets & Competitions
This project is used to examine the actual resolution of a cross talk based TDC. In which, the ZYNQ core is used to provide a reference clock after device start-up. In the meantime, the IDELAY instance inside the LOOP MUX can be adjusted at different tap counts to find out the TDC's resolution. Where, the IDELAY tap delay is determined by comparing it with the reference clock. To be more specific, a crystal clock pulse is brought into the TDC loop by the MMCM.
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450 Views
A pulse stretching Time to Digital Converter (TDC) exploits the crosstalk effect on FPGA routing tracks is proposed. The principle idea is to superpose an induction voltage on the rising edge to lower its logic high toggling point while maintaining the falling edge intact.
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89 Views
A Pulse Stretching Time to Digital Converter(TDC) exploits the crosstalk effect on FPGA. The principle idea is to superpose an induction voltage on the sense line to lower its logic toggling voltage while maintaining the other parameters intact.
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40 Views
A demo for examing the Pulse Shrinking TDC's external capturing performance.
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48 Views
TDC demo for ps level mannual calibration
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68 Views
This design is a Pulse Shrinking TDC with 2ps resolution, which is reduced to 7 CLBs.
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95 Views
Pulse Shrinking TDC utilizing the FPGA cell block Architecture. Ultra Compact Design.
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164 Views