A pulse stretching Time to Digital Converter (TDC) exploits the crosstalk effect on FPGA routing tracks is proposed. The principle idea is to superpose an induction voltage on the rising edge to lower its logic high toggling point while maintaining the falling edge intact.
A Pulse Stretching Time to Digital Converter(TDC) exploits the crosstalk effect on FPGA. The principle idea is to superpose an induction voltage on the sense line to lower its logic toggling voltage while maintaining the other parameters intact.
A demo for examing the Pulse Shrinking TDC's external capturing performance.
This design is a Pulse Shrinking TDC with 2ps resolution, which is reduced to 7 CLBs.
Pulse Shrinking TDC utilizing the FPGA cell block Architecture. Ultra Compact Design.