Two-Fold Reduction of Switching Current Density in Phase Change Memory Using Bi2Te3 Thermoelectric Interfacial Layer
This document shows time-domain thermoreflectance (TDTR) measurements on blanket phase change multilayers [Fig. S1] and electro-thermal simulations of confined PCM cells [Fig. S2]. The extracted thermal resistance per unit area obtained from our measured TDTR signal ratio vs. time delay in Fig. S1 reveals that Bi2Te3 layer only introduces ~13% additional thermal resistance in the PCM stack. On the other hand, Fig. S2 shows the electro-thermal simulation of confined cells with 4 nm Bi2Te3 and 50 nm GST layer with a BE (TiN) diameter of 150 nm in Fig. S2(a) and control device with only 50 nm GST layer in Fig. S2(b). Simulations suggest that confined cell devices have ~20% lower Jreset compared to mushroom cell devices shown in the main text Fig. 4.
The pdf contains figures showing thermal measurements of PCM multilayers (Fig. S1) and electro-thermal simulations of confined PCM cells (Fig. S2). Figure captions and relevant texts in the main manuscript further explain the figures.