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the synthesis results of DC
- Citation Author(s):
- Submitted by:
- Huaqing sun
- Last updated:
- Tue, 05/17/2022 - 22:17
- DOI:
- 10.21227/nr30-na42
- Research Article Link:
- License:
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Abstract
The proposed hardware architecture is modelled by Verilog HDL and synthesized by a Synopsys Design compiler with Semiconductor Manufacturing International Corporation (SMIC) 65-nm CMOS technology. The upload files are the systhesis reports.
Instructions:
The proposed hardware architecture is modelled by Verilog HDL and synthesized by a Synopsys Design compiler with Semiconductor Manufacturing International Corporation (SMIC) 65-nm CMOS technology. The upload files are the reports.
The reports of four transcendental functions are saved in the folder whose name is "reports".
The verilog files of four transcendental functions are saved in the folder whose name is "codes".
The implementation results are listed in the table.
