Supplementary Files - FPGA based Systolic Deconvolution Architecture for Upsampling

Name: Supplementary Files - FPGA based Systolic Deconvolution Architecture for Upsampling
Creator: Alex Noel Joseph raj
License: https://creativecommons.org/licenses/by/4.0/

Citation Author(s):: Alex Noel Joseph Raj (Professor Shantou University)
Submitted by:: Alex Noel Joseph raj
Last updated:: Thu, 04/22/2021 - 13:06
DOI:: 10.21227/rjy7-4f72

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Categories:

Image Processing
Other

Keywords:

FPGA - Deconvolution Architecture- Transpose Convolution

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Abstract

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Instructions:

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Alex Noel Joseph raj Mon, 02/08/2021 - 03:32 Permalink

Dataset Files

Vivado project file for upsampling 4x4 to 8x8 (Size: 167.72 MB)
Vedio for showing different image (Size: 32.44 MB)

DATASET SCRIPTS

Matlab - Upsampling Comparison with various kernel sizes using 4 PE equations

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DATASET TYPE: data
USERID: 1353045
DATASETID: 14627

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Dataset Citation

Alex Noel Joseph Raj, "Supplementary Files - FPGA based Systolic Deconvolution Architecture for Upsampling", IEEE Dataport, February 8, 2021, doi:10.21227/rjy7-4f72

@data{rjy7-4f72-21,
doi = {10.21227/rjy7-4f72},
url = {https://dx.doi.org/10.21227/rjy7-4f72},
author = {Alex Noel Joseph Raj},
publisher = {IEEE Dataport},
title = {Supplementary Files - FPGA based Systolic Deconvolution Architecture for Upsampling},
year = {2021} }

TY - DATA
T1 - Supplementary Files - FPGA based Systolic Deconvolution Architecture for Upsampling
AU - Alex Noel Joseph Raj
PY - 2021
PB - IEEE Dataport
UR - 10.21227/rjy7-4f72
ER -

Alex Noel Joseph Raj (2021). Supplementary Files - FPGA based Systolic Deconvolution Architecture for Upsampling. IEEE Dataport. https://dx.doi.org/10.21227/rjy7-4f72

Alex Noel Joseph Raj 2021 Supplementary Files - FPGA based Systolic Deconvolution Architecture for Upsampling. Available at: https://dx.doi.org/10.21227/rjy7-4f72

Alex Noel Joseph Raj.(2021). "Supplementary Files - FPGA based Systolic Deconvolution Architecture for Upsampling." Web,

1. Alex Noel Joseph Raj. Supplementary Files - FPGA based Systolic Deconvolution Architecture for Upsampling [Internet]. IEEE Dataport; 2021. Available from: https://dx.doi.org/10.21227/rjy7-4f72

Alex Noel Joseph Raj, "Supplementary Files - FPGA based Systolic Deconvolution Architecture for Upsampling,", doi: 10.21227/rjy7-4f72.