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This abstract is based on the work described in the paper (submitted for IEEE Access review) titled "Evaluation of Machine Learning Model Improvement for Hardware Trojan Early Detection on Register Transfer Level Design Using Verilog/VHDL Code Branching Features". The submited dateset consist of 32 different trojan-inserted IP cores design. For each IP core design, the dataset provides some files that contain source code written in VHDL or Verilog design language. Some of the functions inside those files are malicious and some of them are clean.
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The time-to-market pressure and the continuous growing complexity of hardware designs have promoted the globalization of the Integrated Circuit (IC) supply chain. However, such globalization also poses various security threats in each phase of the IC supply chain. Although the advancements of Machine Learning (ML) have pushed the frontier of hardware security, most conventional ML-based methods can only achieve the desired performance by manually finding a robust feature representation for circuits that are non-Euclidean data. As a result, modeling these circuits using graph learning to imp
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