Trust-Hub Trojan Benchmark for Hardware Trojan Detection Model Creation using Machine Learning
This abstract is based on the work described in the paper (submitted for IEEE Access review) titled "Evaluation of Machine Learning Model Improvement for Hardware Trojan Early Detection on Register Transfer Level Design Using Verilog/VHDL Code Branching Features". The submited dateset consist of 32 different trojan-inserted IP cores design. For each IP core design, the dataset provides some files that contain source code written in VHDL or Verilog design language. Some of the functions inside those files are malicious and some of them are clean. The malicious functions usually appear inside a conditional statement that rarely executed. That's why we extract machine learning feature from those conditional statements.
The .xlsx file submitted here (zipped, titled "Benchmark Feature Extraction") contains the result of feature extraction from all conditional statements for each IP cores dataset. This feature extraction process is related to the work described in the manuscript titled "Evaluation of Machine Learning Model Improvement for Hardware Trojan Early Detection on Register Transfer Level Design Using Verilog/VHDL Code Branching Features". You could also extract those features yourself using method described in Chapter IV.A. from the manuscript. To give labels (Trojan/Non-trojan) for each conditional statement branching, you could use Figure 6 from manuscript as reference.