Flip-Flops
![](https://ieee-dataport.org/sites/default/files/styles/3x2/public/tags/images/modern-students-in-university-hall-2021-08-28-15-26-32-utc.jpg?itok=7SJr8zLP)
A novel ultra-low-voltage (ULV) Dual-EdgeTriggered (DET) flip-flop based on the True-Single-PhaseClocking (TSPC) scheme is presented in this paper. Unlike Single-Edge-Triggering (SET), Dual-Edge-Triggering has the advantage of operating at the half-clock rate of the SET clock. We exploit the TSPC principle to achieve the best energy-efficient figures by reducing the overall clock load (only to 8 transistors) and register power while providing fully static, contention-free functionality to satisfy ULV operation.
- Categories:
![](https://ieee-dataport.org/sites/default/files/styles/3x2/public/tags/images/smart-home-3653452_1920.jpg?itok=YlBk8tU8)
The cell characterization scripts and ultra low voltage flip-flop design information including 320-bit (16x20) parallel shift register design....
If you use this data, please add the citation to the following paper :
- Categories: