TL multiplier - supplemental materials

Citation Author(s):
Ratko
Pilipović
Faculty of Computer and Information Science, University in Ljubljana
Submitted by:
Ratko Pilipovic
Last updated:
Sun, 02/14/2021 - 13:48
DOI:
10.21227/cbmz-zz42
Data Format:
License:
0
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Abstract 

This directory contains the Verilog sources of the TL multiplier proposed in the paper entitled ” A two-stage operand trimming approximate logarithmic multiplier”, submitted to TCAS-1.

Instructions: 

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 This code is provided here for research purpose(s) only. For questions and suggestions, please email Ratko Pilipović (ratko.pilipovic@fri.uni-lj.si).

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This directory contains the Verilog sources of our paper,” A two-stage operand trimming approximate logarithmic multiplier”, which is currently under review. 

 

Directory content 

- verilog/8bit  -> Verilog source files for 8-bit  TL multipliers 

- verilog/16bit -> Verilog source files for 16-bit TL multipliers 

- verilog/24bit -> Verilog source files for 24-bit TL multipliers 

- verilog/32bit -> Verilog source files for 32-bit TL multipliers

 

- synthesis/src/* -> Verilog code of TL16/8-4 

- synthesis/constraint.sdc -> Used constraints in synthesis 

- synthesis/config.mk -> Used configuration in synthesis

 - synthesis/reports/* -> output files from different stages of OpenROAD synthesis flow, including the final GDS file 

- synthesis/reports/* -> output files from different stages of OpenROAD synthesis flow, including the final GDS file