Datasets
Standard Dataset
TL multiplier - supplemental materials
- Citation Author(s):
-
RatkoPilipović
Faculty of Computer and Information Science, University in Ljubljana - Submitted by:
- Ratko Pilipovic
- Last updated:
- Tue, 05/17/2022 - 22:18
- DOI:
- 10.21227/cbmz-zz42
- Data Format:
- Research Article Link:
- License:
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Abstract
This code is provided here for research purpose(s) only. You are allowed to use this code/data provided that you cite the following papers:
R. Pilipović and P. Bulić, "On the Design of Logarithmic Multiplier Using Radix-4 Booth Encoding," in IEEE Access, vol. 8, pp. 64578-64590, 2020, doi: 10.1109/ACCESS.2020.2985345.
R. Pilipović, P. Bulić, and U.Lotrič, "A two-stage operand trimming approximate logarithmic multiplier" in IEEE Transactions on Circuits and Systems I: Regular Papers, 2021.
For questions and suggestions, please email Ratko Pilipović (ratko.pilipovic@fri.uni-lj.si).
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This code is provided here for research purpose(s) only. For questions and suggestions, please email Ratko Pilipović (ratko.pilipovic@fri.uni-lj.si).
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This directory contains the Verilog sources of our paper,” A two-stage operand trimming approximate logarithmic multiplier”, which is currently under review.
Directory content
- verilog/8bit/ -> Verilog source files for 8-bit TL multipliers
- verilog/16bit/ -> Verilog source files for 16-bit TL multipliers
- verilog/24bit/ -> Verilog source files for 24-bit TL multipliers
- verilog/32bit/ -> Verilog source files for 32-bit TL multipliers
- synthesis/src/ -> Verilog code of TL16/8-4
- synthesis/constraint.sdc -> Used constraints in synthesis
- synthesis/config.mk -> Used configuration in synthesis
- synthesis/reports/ -> output files from different stages of OpenROAD synthesis flow, including the final GDS file
- synthesis/reports/ -> output files from different stages of OpenROAD synthesis flow, including the final GDS file
