LOBO multiplier - supplemental materials

Citation Author(s):
Ratko
Pilipovic
Faculty of Computer and Information Science, University in Ljubljana
Submitted by:
Ratko Pilipovic
Last updated:
Mon, 04/05/2021 - 04:11
DOI:
10.21227/1fx5-5207
License:
0
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Abstract 

This code is provided here for research purpose(s) only. You are allowed to use this code/data provided that you cite the following papers:

 

R. Pilipović and P. Bulić, "On the Design of Logarithmic Multiplier Using Radix-4 Booth Encoding," in IEEE Access, vol. 8, pp. 64578-64590, 2020, doi: 10.1109/ACCESS.2020.2985345.

  

For questions and suggestions, please email Ratko Pilipović (ratko.pilipovic@fri.uni-lj.si).

Instructions: 

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 This code is provided here for research purpose(s) only. For questions and suggestions, please email Ratko Pilipović (ratko.pilipovic@fri.uni-lj.si).

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This directory contains the Verilog sources of our paper,” A two-stage operand trimming approximate logarithmic multiplier”, which is currently under review. 

 

Directory content 

  • verilog/LOBO_16bit/ -> Verilog source files for 16-bit LOBO multipliers
  • verilog/LOBO_24bit/ -> Verilog source files for 24-bit LOBO multipliers
  • verilog/LOBO_32bit/ -> Verilog source files for 32-bit LOBO multipliers
  • synthesis/src/ -> Verilog code of LOBO_12_12_8
  • synthesis/constraint.sdc ->  Used constraints in synthesis
  • synthesis/config.mk -> Used configuration in synthesis
  • synthesis/reports/ -> output files from different stages of OpenROAD synthesis flow, including the final GDS file 
  • synthesis/reports/ -> output files from different stages of OpenROAD synthesis flow, including the final GDS file