Energy-efficient processing.
Contains data supporting the IEEE TC submission titled "General Principles for Implementing Branch Prediction in Fully Adiabatic, Reversible, and SuperScalar (FARS) Processors". Paper abstract: Adiabatic and reversible logic families take advantage of Landauer's principle to provide a more efficient means of computation using conventional MOSFETs. However, there are performance drawbacks inherent in the way such devices physically operate. Such drawbacks can be overcome by scaling the number of devices to meet performance needs.
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This code is provided here for research purpose(s) only. You are allowed to use this code/data provided that you cite the following papers:
R. Pilipović and P. Bulić, "On the Design of Logarithmic Multiplier Using Radix-4 Booth Encoding," in IEEE Access, vol. 8, pp. 64578-64590, 2020, doi: 10.1109/ACCESS.2020.2985345.
R. Pilipović, P. Bulić, and U.Lotrič, "A two-stage operand trimming approximate logarithmic multiplier" in IEEE Transactions on Circuits and Systems I: Regular Papers, 2021.
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