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First Name: 
Sanjiv
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Sambandan

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The reliability of In-Si-O (ISO) thin-film transistors (TFT) to bias voltage-stress and photo-stress is studied. The ISO TFTs were developed with a fully photolithographic process, with a maximum temperature of 200 C. The TFTs typically showed a mobility of 5.03 cm$^2$/Vs, a threshold voltage, $V_{th}$, of -0.16 V and a subthreshold swing of 312 mV/dec. The TFTs were biased for up to four hours at different temperatures and illumination. Threshold voltage shifts were observed and modeled.

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The impact of high curvature bending on thin film transistor(TFT) performance is of interest for flexible electronics. Bending influences TFT performance in two ways. First due to mechanical stress and second due to the pure geometric effect of converting a planar architecture to a cylindrical one. Experiments to simultaneously create and yet distinguish these two effects are difficult. Analytical models are required to identify the individual impact of stress and geometry. The goal of this work is to identify the purely geometrical impact on TFT characteristics.

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