Datasets
Standard Dataset
MESO standard cell models
- Citation Author(s):
- Submitted by:
- Tzuping Huang
- Last updated:
- Thu, 12/12/2024 - 22:41
- DOI:
- 10.21227/stw7-8b36
- Data Format:
- License:
20 Views- Categories:
- Keywords:
Abstract
The proposed SystemVerilog MESO models offer significantly faster simulation capabilities compared to the physical model [1], improving simulation speed while preserving essential accuracy. This enhancement enables the design of more complex circuits, including MESO cells, standard cells, and intellectual property (IP) blocks, while incorporating time multiplexing techniques.
The development of this MESO-based standard cell library follows a systematic process: first, the basic MESO cell is simulated using a physical SPICE and Verilog-A model to measure key parameters, such as transition time. Next, a behavioral MESO cell model is created in SystemVerilog based on these parameters. Following this, a behavioral MESO-based majority gate is designed. Finally, behavioral MESO-based standard cells, including OR, NOR, AND, and NAND gates, are constructed using the MESO-based majority gate.
After downloading the files, the user can uncompress them using tar and unzip to review the content.
To run simulations using the provided models, please follow the steps below.
1. Edit the file list to ensure all necessary SystemVerilog models are included in vflist.sv
2. Run the simulation using the Cadence tool Xcelium on a Linux system with the following command: xrun -64 +v2k +access+rwc vflist.sv
3. The simulation generates two output files: a log file (xrun.log) and a waveform file (meso.fsdb).
4. To review the simulation results using nWave, execute the following Linux command: nWave &
