Verilog-a
The proposed SystemVerilog MESO models offer significantly faster simulation capabilities compared to the physical model [1], improving simulation speed while preserving essential accuracy. This enhancement enables the design of more complex circuits, including MESO cells, standard cells, and intellectual property (IP) blocks, while incorporating time multiplexing techniques.
- Categories:
7 Views
This dataset is a Verilog-a implementation of a dynamic compact model of ferroelectric capacitance. It can be run with a SPICE-type circuit simulator.
Researchers using this dataset should cite it as follows: Ning Feng, Hao Li, Chang Su, Lining Zhang, Qianqian Huang,Runsheng Wang, and Ru Huang, A Dynamic Compact Model for Ferroelectric Capacitance, IEEE Electron Device Letters, DOI: 10.1109/LED.2022.3141413
- Categories:
257 Views