Verilog-a

This dataset is a Verilog-a implementation of a dynamic compact model of ferroelectric capacitance. It can be run with a SPICE-type circuit simulator. 

Researchers using this dataset should cite it as follows: Ning Feng, Hao Li, Chang Su, Lining Zhang, Qianqian Huang,Runsheng Wang, and Ru Huang,  A Dynamic Compact Model for Ferroelectric Capacitance, IEEE Electron Device Letters, DOI: 10.1109/LED.2022.3141413