PUF-Enhanced Processor Design for Image Encryption (datasets)

Citation Author(s):
Zhuoheng
Ran
University of Southampton
Submitted by:
ZHUOHENG RAN
Last updated:
Sun, 11/20/2022 - 13:13
DOI:
10.21227/av21-9015
License:
Creative Commons Attribution
211 Views
Categories:
Security
Image Processing
Keywords:
Physically unclonable functions, image encryption, RISC processor, multi-core system, affine transform, FPGA.
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Abstract 

PUF-Enhanced Processor Design for Image Encryption (datasets).

All the hardware experimental data were collected from 8 equal FPGA development kits and a test manual is included.

Devices: Artix-7 FPGA (XC7A100TCSG324-1). IDE Version: Vivado-2020.1.

Instructions: 

The test manual describes how to test this design.

Dataset Files

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Documentation

AttachmentSize
File Test manual.pdf237.51 KB

 

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