PUF-Enhanced Processor Design for Image Encryption (datasets)
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- ZHUOHENG RAN
- Last updated:
- Sun, 11/20/2022 - 13:13
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PUF-Enhanced Processor Design for Image Encryption (datasets).
All the hardware experimental data were collected from 8 equal FPGA development kits and a test manual is included.
Devices: Artix-7 FPGA (XC7A100TCSG324-1). IDE Version: Vivado-2020.1.
The test manual describes how to test this design.
- Datasets_Ran.zip (14.79 MB)