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Multi-Gate In-plane Actuated NEMS Relays for Effective Complementary Logic Gate Designs Figure Data
- Citation Author(s):
- Submitted by:
- Bennett Smith
- Last updated:
- Thu, 07/06/2023 - 17:20
- DOI:
- 10.21227/tgbr-hd45
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- License:
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Abstract
Data used to produce figures 5-7 in the paper Multi-Gate In-plane Actuated NEMS Relays for Effective Complementary Logic Gate Designs as well as tables 1 and 2. Figure 5 shows input and output data collected from a 3-input NAND gate comprised of a novel multi-gate (multi-input relay). Figures 6 and 7 present data from COMSOL simulations indended to outline a procedere for optimizing these relays and allow for scaling of the device parameters. Table 1 compares our designs with those of other works, in terms of number of relays and critical path. Table 2 compares the parameters of actual fabricated structures with those of the simulations.
The dataset is divided into blocks of what was used for each figure. Figure 5 is comprised of 16 panels which are each plots of voltage vs time. The column identifiers indicate the voltage level supplied across the four tests (low, medium, high, higher) while the letters indicate which terminal the input signal was supplied to (a = smallest, c = largest). The collumns indicated as Vout, contain the subsequent output voltage data. Figure 6 is plotted to show the effects on pull-in voltage (y-axis), by altering the gate length and position respectively. Figure 7 contains simulation data for optimized cantilevers. Cantilevers optimized with a minimum gate length of 0.85 microns are marked as normal. Columns scaled for larger values of LA are marked as Wide. The gate lengths and pull-in voltages are given. Table 1 is identical data to what is shown in the paper. Table 2 contains the measured relay pull-in voltage data. Below it is the COMSOL simulated data and the standard deviation from the average.
