Hardware Design; Hardware Trojan Detection; RTL

This abstract is based on the work described in the paper (submitted for IEEE Access review) titled "Evaluation of Machine Learning Model Improvement for Hardware Trojan Early Detection on Register Transfer Level Design Using Verilog/VHDL Code Branching Features". The submited dateset consist of 32 different trojan-inserted IP cores design. For each IP core design, the dataset provides some files that contain source code written in VHDL or Verilog design language. Some of the functions inside those files are malicious and some of them are clean.