Physical Unclonable Function
This dataset contains Challenge-Response Pairs (CRPs) from Ring Oscillator-based Physical Unclonable Functions (RO-PUFs) operating under constant and variable voltage conditions. Collected from three chips fabricated in a 22nm FDSOI process and powered by a Switched-Capacitor DC-DC converter, it includes two sections: responses at a fixed voltage and across nine voltage levels (nominal and ±10% variations). Organized into ten folders, the dataset includes 1K CRPs per chip for each voltage and a combined folder with 20K CRPs.
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data for different PUF designs that has been implemented on different FPGA for making a final comparision Table for new PUF disigns and some conventional ones. These data can be useful for any Hardware security implementation to make the decision regarding a PUF. These can be used when anyone need to extract Crptographic KEY.
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This data set corresponds to Table II:UNIFORMITY OF TC-PUF DESIGN of manuscript titled "A Lightweight and Secure Physical Unclonable Function Design on FPGA". The provided data is for FPGA board No. 1 to 15. Board no. 1 to 14 represent uniformity of 40X40 TC-PUF response implemented on Artix-7 FPGA, and board no. 15 represent uniformity of 20X40 TC-PUF response implemented on Zynq Z-7010 FPGA. It is observed that nearly all the TC-PUF implemented on individual FPGAs have a slight bias towards ‘0’.
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