Optical Emission Spectroscopy (OES)
Maintaining etch uniformity from the center to the edge of the wafer during the etching process is a critical challenge. In particular, the edge of the wafer poses difficulties due to changes in the angle of ion incidence caused by the curvature of the sheath, making it challenging to achieve the desired etch pattern. Therefore, identifying and monitoring key factors that significantly impact center-to-edge uniformity is essential.
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The SiO2 etching process using CF4/O2 plasma is a critical step in semiconductor manufacturing, where process efficiency and precise control are essential. In this study, optical emission spectroscopy (OES) data was utilized in real-time to analyze the correlation between plasma conditions and the etch rate (ER) during the process. Specifically, the source and bias power were divided into four different conditions to systematically evaluate the changes in plasma characteristics and the etching process. Based on this evaluation, a physical model was developed to predict the etch rate.
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As semiconductor devices have become increasingly miniaturized, the ability to control very small Critical Dimensions (CDs) during the etching process has become crucial through controlled plasma processes. Consequently, diagnosing plasma and reflecting this in the process to enhance yield is of paramount importance. Typically, an invasive sensor like a Single Langmuir Probe (SLP) is utilized for plasma diagnostics. However, using this sensor can affect the plasma, necessitating the use of non-invasive diagnostic methods.
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As semiconductor devices have become increasingly miniaturized, the ability to control very small Critical Dimensions (CDs) during the etching process has become crucial through controlled plasma processes. Hence, diagnosing plasma and reflecting this in the process to enhance yield is of paramount importance. Typically, a Single Langmuir Probe (SLP) is utilized for plasma diagnostics.
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Recent semiconductor devices have embraced structural modifications, including vertical stacking, to overcome the limitations of miniaturization. Particularly, memory devices have seen improvements through the transition to 3D stack structures. To address the challenges of etching high aspect ratio contact holes, the Bosch process, which alternates between deposition of a passivation layer on the pattern wall to prevent sidewall etching and etching steps, has been utilized.
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