MIS NAND/NOR simulations

Citation Author(s):
Shashank Ram
Submitted by:
Shashank Ram O.V.S
Last updated:
Thu, 05/28/2020 - 06:58
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Traditional Static Timing Analysis (STA) assumes only single input switches at a time with the side input held at non-controlling value. This introduces unnecessary pessimism or optimism which may cause degradation of performance or chip failure.  Modeling Multi-Input Switching (MIS) requires a good amount of simulations hence we provide a dataset comprising of SPICE simulations done on 2 input NAND and NOR gate. The simulations are done in a Multi-Input Switching Scenario, where both the inputs switch simultaneously simulations using NANGATE FreePDK 15nm library and models on a parasitics extracted netlist.


This dataset consists of the simulations of 2 input NAND and NOR gates in the Multi-Input Switching (MIS) scenario.

tr1 and tr2 denote the input transitions, D denote the skew/ temporal proximity between the two inputs and C denotes the Capacitive load.

The outputs comprise the gate delay and output transitions for both rise and fall cases. Both MIS and SIS (single input switching) values are provided.

PVT_MIS consists of simulations at 3 different corners for NAND and NOR gates with typical STA tool and Golden SPICE.