MIS NAND/NOR simulations

Traditional Static Timing Analysis (STA) assumes only single input switches at a time with the side input held at non-controlling value. This introduces unnecessary pessimism or optimism which may cause degradation of performance or chip failure.  Modeling Multi-Input Switching (MIS) requires a good amount of simulations hence we provide a dataset comprising of SPICE simulations done on 2 input NAND and NOR gate. The simulations are done in a Multi-Input Switching Scenario, where both the inputs switch simultaneously simulations using NANGATE FreePDK 15nm library and models on a parasitics extracted netlist.