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First Name:
Li
Last Name:
Ding
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Interleaving three-phase voltage source converters (VSCs) is a popular solution for medium- and high-power applications. In addition to the circulating current, the impact of PWM strategies on the DC-link current ripple is an important issue for practical DC-link capacitor designs, which could affect system reliability and lifetime. Existing studies have been reported to evaluate the impact of conventional pulse width modulation (PWM) strategies such as space vector modulation (SVM), sinusoidal PWM (SPWM), and discontinuous PWM (DPWM).
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This paper proposed an optimized zero-state replacement (ZSR) method for general Bi-tri logic SPWM (BTSPWM) to deal with the common-mode voltage (CMV) issue. The BTSPWM can take advantage of the well-developed modulation strategies adopted in voltage source converters (VSCs) and transfer them into a current source converter (CSC) system through logic translation, which shares more general features compared with other modulations developed for CSC.
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