Verilog source files

This code is provided here for research purpose(s) only. You are allowed to use this code/data provided that you cite the following papers:

R. Pilipović and P. Bulić, "On the Design of Logarithmic Multiplier Using Radix-4 Booth Encoding," in IEEE Access, vol. 8, pp. 64578-64590, 2020, doi: 10.1109/ACCESS.2020.2985345.

R. Pilipović, P. Bulić, and U.Lotrič, "A two-stage operand trimming approximate logarithmic multiplier" in IEEE Transactions on Circuits and Systems I: Regular Papers, 2021.