10 Gb/s Duobinary Transmitter with a 6-Tap FFE in 180 nm CMOS

A duobinary transmitter has been realized in this paper. The combination of high-frequency compensation characteristics of 6-tap feed forward equalizer (FFE) and high frequency attenuation characteristics of FR4 backplane is used to produce duobinary signal. 5-stage calibrated delay unit with source capacitance degeneration is used to achieve a delay of 100 ps. The load resistance, source resistance and source capacitor are used to improve the flatness of group delay of delay unit. A prototype chip fabricated in 180 nm CMOS process has an area of 0.544 mm2 with an energy efficiency of 19.4 pJ/bit. At the output of 18-inch FR4 backplane whose insertion loss is 16.5 dB, an eye diagram of duobinary signal with an opening of 45 mV can be obtained.