FPGA project

This project is used to examine the actual resolution of a cross talk based TDC. In which, the ZYNQ core is used to provide a reference clock after device start-up. In the meantime, the IDELAY instance inside the LOOP MUX can be adjusted at different tap counts to find out the TDC's resolution. Where, the IDELAY tap delay is determined by comparing it with the reference clock. To be more specific, a crystal clock pulse is brought into the TDC loop by the MMCM.