This research examined the electrical characteristics
of a conventional junctionless silicon-on-insulator (SOI-JL) and a
SOI hybrid P/N fin channel JL thin film transistor (SOI-H-JL)
using a simulation with gate lengths from 60 nm to 10 nm. The
interface location of the SOI-H-JL has a depletion region of a
parallel channel, which influences the effective thickness of the
channel. The threshold voltage can be adjusted by changing the
concentration of the substrate. Better electrical characteristics