Phase-locked loop (PLL)
These controller design and simulation files correspond to the paper "A Multivariable Controller in Synchronous Frame Integrating Phase-Locked Loop to Enhance Performance of Three-Phase Grid-connected Inverters in Weak Grids" which presents a new current controller in the synchronous reference frame and its associated design for enhancing the performance of three-phase grid-connected inverters, especially against weak-grid conditions.
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This paper presents approaches for efficient modeling and systematic design of enhanced phase-locked loop (ePLL) structures. While different ePLL structures have found a wide acceptance for various applications, their modeling and design aspects have not been fully and systematically reported in existing references. This paper fills this gap by presenting an effective modeling approach for both single-phase and threephase ePLLs. The models are derived with a view to minimize the number of parameters to be adjusted to simplify the design.
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