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An Investigation of the Scalability of a 3D Stacked Hybrid P/N Layer and Vertical Gate SOI Junctionless FET
- Citation Author(s):
- Cheng-Kuei Lee, Sen Yin, Jin-Yu Zhang, Zuo-Chang Ye,Yan Wang nad Zhi-ping Yu
- Submitted by:
- Sen Yin
- Last updated:
- Thu, 11/08/2018 - 10:34
- DOI:
- 10.21227/m6xf-3898
- License:
93 Views- Categories:
- Keywords:
Abstract
This research examined the electrical characteristics
of a conventional junctionless silicon-on-insulator (SOI-JL) and a
SOI hybrid P/N fin channel JL thin film transistor (SOI-H-JL)
using a simulation with gate lengths from 60 nm to 10 nm. The
interface location of the SOI-H-JL has a depletion region of a
parallel channel, which influences the effective thickness of the
channel. The threshold voltage can be adjusted by changing the
concentration of the substrate. Better electrical characteristics
and higher transconductance can be obtained under the short
channel when compared with the conventional SOI-JL. Although
the hybrid structure has better electrical characteristics, the
larger gate capacitance results in the delay time excessively long
as a defect, which can be improved by thickening the raised
source/drain area. The circuit performance is evaluated by
building up an inverter using aforementioned devices.
This research examined the electrical characteristics
of a conventional junctionless silicon-on-insulator (SOI-JL) and a
SOI hybrid P/N fin channel JL thin film transistor (SOI-H-JL)
using a simulation with gate lengths from 60 nm to 10 nm. The
interface location of the SOI-H-JL has a depletion region of a
parallel channel, which influences the effective thickness of the
channel. The threshold voltage can be adjusted by changing the
concentration of the substrate. Better electrical characteristics
and higher transconductance can be obtained under the short
channel when compared with the conventional SOI-JL. Although
the hybrid structure has better electrical characteristics, the
larger gate capacitance results in the delay time excessively long
as a defect, which can be improved by thickening the raised
source/drain area. The circuit performance is evaluated by
building up an inverter using aforementioned devices.
Documentation
| Attachment | Size |
|---|---|
 TED-初稿-6-zhang(8.7).pdf | 1.11 MB |
Comments
A SOI hybrid thin-film transistor inherits the merits of both
SOI and bulk transistors. The doping concentration of the
substrate can be used for controlling VTH. Simulation results
show that SOI-H-JL and SOI-DH-JL structures have better
inhibitory effects on SCE and higher ION/IOFF ratio. For the two
structures under a low gate voltage, the carrier concentration of
the channel center was found to be affected by the depletion
area, which results in a smaller IOFF than the conventional
SOI-JL. Furthermore, the SOI-DH-JL structure is composed of
double channels, increasing the saturation current and gm.
Although the hybrid structure has better electrical properties,
the intrinsic capacitance is quite large originated from extra PN
junctions and large coverage areas under gate. This results in a
disadvantage that may potentially have an impact on the
transmission delay. Thickening of raised S/D area can be used
for reducing the delay time. Inverter performance shows that
SOI-JL has better delay time, but SOI-DH-JL has more
advantages in noise margin.