Supplementary Material of DrlGoFPGA

This supplementary material provides the clock routing constraint analysis for each design on ISPD'2017 benchmarks, as well as the specific HPWL and GPT values for each design on MLCAD 2023 benchmarks based on DREAMPlaceFPGA-MP, OpenPARF 3.0, and DrlGo-Design_1-PT. In addition, this supplementary material also provides the experimental results on the effect of different reward function designs and different combinations of NNs and GNNs on solution performance.