The proposed hardware architecture is modelled by Verilog HDL and synthesized by a Synopsys Design compiler with Semiconductor Manufacturing International Corporation (SMIC) 65-nm CMOS technology. The upload files are the systhesis reports.

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[1] Huaqing Sun, "the synthesis results of DC", IEEE Dataport, 2019. [Online]. Available: http://dx.doi.org/10.21227/nr30-na42. Accessed: Feb. 17, 2025.
@data{nr30-na42-19,
doi = {10.21227/nr30-na42},
url = {http://dx.doi.org/10.21227/nr30-na42},
author = {Huaqing Sun },
publisher = {IEEE Dataport},
title = {the synthesis results of DC},
year = {2019} }
TY - DATA
T1 - the synthesis results of DC
AU - Huaqing Sun
PY - 2019
PB - IEEE Dataport
UR - 10.21227/nr30-na42
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Huaqing Sun. (2019). the synthesis results of DC. IEEE Dataport. http://dx.doi.org/10.21227/nr30-na42
Huaqing Sun, 2019. the synthesis results of DC. Available at: http://dx.doi.org/10.21227/nr30-na42.
Huaqing Sun. (2019). "the synthesis results of DC." Web.
1. Huaqing Sun. the synthesis results of DC [Internet]. IEEE Dataport; 2019. Available from : http://dx.doi.org/10.21227/nr30-na42
Huaqing Sun. "the synthesis results of DC." doi: 10.21227/nr30-na42