Pulse Shrinking TDC utilizing the FPGA cell block Architecture. Ultra Compact Design.

DOI Link: 
10.21227/svj3-8h11
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vivado project
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[1] Li Xiang, "Pulse Shrinking TDC Vivado Project", IEEE Dataport, 2021. [Online]. Available: http://dx.doi.org/10.21227/svj3-8h11. Accessed: Feb. 17, 2025.
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doi = {10.21227/svj3-8h11},
url = {http://dx.doi.org/10.21227/svj3-8h11},
author = {Li Xiang },
publisher = {IEEE Dataport},
title = {Pulse Shrinking TDC Vivado Project},
year = {2021} }
TY - DATA
T1 - Pulse Shrinking TDC Vivado Project
AU - Li Xiang
PY - 2021
PB - IEEE Dataport
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Li Xiang. (2021). Pulse Shrinking TDC Vivado Project. IEEE Dataport. http://dx.doi.org/10.21227/svj3-8h11
Li Xiang, 2021. Pulse Shrinking TDC Vivado Project. Available at: http://dx.doi.org/10.21227/svj3-8h11.
Li Xiang. (2021). "Pulse Shrinking TDC Vivado Project." Web.
1. Li Xiang. Pulse Shrinking TDC Vivado Project [Internet]. IEEE Dataport; 2021. Available from : http://dx.doi.org/10.21227/svj3-8h11
Li Xiang. "Pulse Shrinking TDC Vivado Project." doi: 10.21227/svj3-8h11