Impact of Substrate Bias on Analog Performance of Dopingless Transistor
In this brief, the impact of substrate bias (Vgb), on the electrical performance of silicon on insulator dopingless transistor (SOI-DLT) is analysed for analog applications. It is observed that SOI-DLTs are more immune to Vgb in contrast to its conventional counterpart SOI junctionless transistor (SOIJLT). When Vgb is increased from 2V to 8V, the variation in intrinsic gain (gmrO) of SOI-JLT is 81.69%, however, in the case of SOI-DLT, the gmrO variation is 5.37%. The insignificant variation in gmrO of SOI-DLT is found against Vgb than SOI-JLT due to the use of the lightly doped channel. Further, the device reliability of SOI DLT against impact ionization is evaluated by measuring the electron concentration and electric field profile. The SOI-DLT is less sensitive to impact ionization in comparison to conventional SOI-JLT. Hence, the simulation results shown in this paper offer an opportunity for future analog integrated circuits designing by using SOI-DLT under the influence of Vgb.
Description: We have analyzed the impact of substrate voltage on the analog performance of SOI-dopingless transistor and compared it with SOI-junctionless transistor.
Size: The total size of all objects is 30.4MB.
Environment: The windows 10 Home environment is used. We have investigated the device performance using 2-D device ATLAS simulator version 5.2.8. The Origin Pro 2021b (64-bit) SR2 version 188.8.131.52 is used for adjusting graph.
Detailed setup instructions: We have written the code in deck build 2-D device ATLAS simulator and for this first, we have set device parameters like High-K oxide thickness (tox) is 2nm and HfO2 under S/D region (tox2) is 1nm, channel thickness (tsi) is varying from 6nm-10nm, gate length (tch) is varying from 10nm-30nm and substrate region thickness is 120nm. We have taken origin in the mid of the device. MOS is a symmetrical device. So, when we set gate length (tch) is equal to 15nm, the effective gate length is 30nm.
Further, we have taken meshing in x-direction and y-direction after that give region name for substrate, BOX, spacer, source, drain, and gate. We have given contact names for gate, source, drain and substrate further provide doping concentration for substrate region is 5×1018 cm-3 and channel region 1×1015 cm-3. The work function for the gate is 4.72 and for the formation of S/D is 3.9. We analyzed transconductance (gm), threshold voltage (VTH) values for different substrate voltages. We also find ID-VDScurve for rO calculation. after simulation, we get two type files with extension names *.log and *.str. *.log files contain graphical information and *.str is contain structural information. To find the probability of impact ionization, we need lateral electric field and electron concentration profile near the drain region, to obtain this we have to open *.str file and data exported in MS excel.
After collecting these data, we saved in MS excel file and further we graph plotted in origin pro 2021b software.
Detailed run instructions: We have used 2-D device ATLAS simulator version 5.2.8.R, its extension file name is *.in after simulation another two files is generated with extension name is *.log and *.str. All graphical data details in *.log file and all structural details in *.str file. Tonyplot is ATLAS graph simulator. Tonyplot graph data exported into MS Excel sheet. Further, copy these excel data and use origin Pro 2021b (64-bit) SR2 version 184.108.40.206 to plot the graph.
Output description: For any analog amplifier we need high transconductance (gm), intrinsic gain (gmrO), and low threshold voltage (VT) but these parameters value is sensitive to substrate voltage (Vgb). We have shown SOI-DLT have less sensitive towards Vgb as compare to SOI-JLT. We have also analyzed the effect of gate-length (Lg) and channel-thickness (tsi) over gm and VT and the probability of impact ionization. We found SOI-DLT is less sensitive toward substrate voltage.
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